WinAPE Assembler Z80 Support
Z80 Registers
The assembler supports all standard Z80 8 bit registers A, B, C, D, E, H, L and special 8 bit registers I and R. It also supports all standard Z80 16 bit registers AF, BC, DE, HL and SP and index registers IX and IY. For one instruction EX AF,AF' the alternate AF' register is also supported.
WinAPE also supports the undocumented use of the 8 bit portions of the IX and IY registers, these registers may be entered as HX or IXh, LX or IXl, HY or IYh and LY or IYl. References below will use the first versions (HX, LX, HY and LY) although they apply equally to the alternate version.
Z80 Conditions
The assembler supports all Z80 conditions NZ, Z, NC, C, PO, PE, P and M.
Z80 Instructions
All the standard Z80 instructions are supported with some additional support for undocumented instructions or register usage. The following table lists all Z80 instructions supported. The assembler is NOT case-sensitive.
| Instruction | Description |
| ADC A,r | 1 Add with Carry (r = A, B, C, D, E, H, L, HX, HY, LX or LY) |
| ADC A,n | 1 n is a byte |
| ADC A,(HL) | 1 |
| ADC A,(IX + d) | 1,2 d is signed displacement |
| ADC A,(IY + d) | 1,2 |
| ADC HL,ss | (ss = BC, DE, HL or SP) |
| ADD A,r | 1 Add (r = A, B, C, D, E, H, L, HX, HY, LX or LY) |
| ADD A,n | 1 n is a byte |
| ADD A,(HL) | 1 |
| ADD A,(IX + d) | 1,2 d is signed displacement |
| ADD A,(IY + d) | 1,2 |
| ADD HL,ss | (ss = BC, DE, HL or SP) |
| ADD IX,pp | (pp = BC, DE, IX or SP) |
| ADD IY,rr | (pp = BC, DE, IY or SP) |
| AND A,r | 1 (r = A, B, C, D, E, H, L, HX, HY, LX or LY) |
| AND A,n | 1 n is a byte |
| AND A,(HL) | 1 |
| AND A,(IX + d) | 1,2 d is signed displacement |
| AND A,(IY + d) | 1,2 |
| BIT b,r | Test Bit b (b = 0 .. 7, r = B, C, D, E, H, L or A) |
| BIT b,(HL) | |
| BIT b,(IX + d) | 2 |
| BIT b,(IY + d) | 2 |
| CALL nn | Call Subroutine at nn |
| CALL cc,nn | Call on Condition (cc = NZ, Z, NC, C, PO, PE, P or M) |
| CCF | Complement Carry Flag |
| CP A,r | 1Compare (r = A, B, C, D, E, H, L, HX, HY, LX or LY) |
| CP A,n | 1 n is a byte |
| CP A,(HL) | 1 |
| CP A,(IX + d) | 1,2 d is signed displacement |
| CP A,(IY + d) | 1,2 |
| CPD | Compare with Decrement |
| CPDR | |
| CPI | Compare with Increment |
| CPIR | |
| CPL | Complement Accumulator |
| DAA | Decimal Adjust Accumulator |
| DEC r | Decrement (r = A, B, C, D, E, H, L, HX, HY, LX or LY) |
| DEC (HL) | |
| DEC (IX + d) | 2 |
| DEC (IX + d) | 2 |
| DEC ss | (ss = BC, DE, HL, SP, IX or IY) |
| DI | Disable Interrupts |
| DJNZ e | 5 |
| EI | Enable Interrupts |
| EX AF,AF' | |
| EX DE,HL | Can also be written as EX HL,DE |
| EX (SP),HL | |
| EX (SP),IX | |
| EX (SP),IY | |
| EXX | |
| HALT | |
| IM 0 | Interrupt Mode 0 |
| IM 1 | Interrupt Mode 1 |
| IM 2 | Interrupt Mode 2 |
| IN A,(n) | Input from Port n. The A register is used for the top 8 bits of the address bus. |
| IN r,(C) | Input from Port BC (r = B, C, D, E, H, L or A) |
| INC r | Increment (r = A, B, C, D, E, H, L, HX, HY, LX or LY) |
| INC (HL) | |
| INC (IX + d) | 2 |
| INC (IX + d) | 2 |
| INC ss | (ss = BC, DE, HL, SP, IX or IY) |
| IND | Input with Decrement |
| INDR | |
| INI | Input with Increment |
| INIR | |
| JP nn | Jump to Address nn |
| JP cc,nn | Jump on Condition (cc = NZ, Z, NC, C, PO, PE, P or M) |
| JP (HL) | Jump to HL |
| JP (IX) | Jump to IX |
| JP (IY) | Jump to IY |
| JR e | 5 Jump Relative, calculated address must be within -126 to +130 of instruction address. |
| JR ss,e | 5 (ss = NZ, Z, NC or C) |
| LD r,r' | 3 Load register (r/r' = A, B, C, D, E, H, L, HX, HY, LX or LY) |
| LD r,n | Load register (r = A, B, C, D, E, H, L, HX, HY, LX or LY) |
| LD r,(HL) | (r = A, B, C, D, E, H or L) |
| LD r,(IX + d) | 2 (r = A, B, C, D, E, H or L) |
| LD r,(IY + d) | 2 (r = A, B, C, D, E, H or L) |
| LD (HL),r | (r = A, B, C, D, E, H or L) |
| LD (IX + d),r | 2 (r = A, B, C, D, E, H or L) |
| LD (IY + d),r | 2 (r = A, B, C, D, E, H or L) |
| LD (HL),n | |
| LD (IX + d),n | 2 |
| LD (IY + d),n | 2 |
| LD A,(BC) | |
| LD A,(DE) | |
| LD A,(nn) | |
| LD (BC),A | |
| LD (DE),A | |
| LD (nn),A | |
| LD A,I | |
| LD A,R | |
| LD I,A | |
| LD R,A | |
| LD dd,nn | (dd = BC, DE, HL, SP, IX or IY) |
| LD dd,(nn) | (dd = BC, DE, HL, SP, IX or IY) |
| LD (nn),dd | (dd = BC, DE, HL, SP, IX or IY) |
| LD SP,HL | |
| LD SP,IX | |
| LD SP,IY | |
| LDD | Load with Decrement |
| LDDR | |
| LDI | Load with Increment |
| LDIR | |
| NEG | Negate Accumulator |
| NOP | No Operation |
| OR A,r | 1 (r = A, B, C, D, E, H, L, HX, HY, LX or LY) |
| OR A,n | 1 n is a byte |
| OR A,(HL) | 1 |
| OR A,(IX + d) | 1,2 d is signed displacement |
| OR A,(IY + d) | 1,2 |
| OTDR | Repeated Output with Decrement |
| OTIR | Repeated Output with Increment |
| OUT (n),A | Output to Port n. The A register is used for the top 8 bits of the address bus. |
| OUT (C),r | Output to Port BC (r = B, C, D, E, H, L or A) |
| OUTD | Output with Decrement |
| OUTI | Output with Increment |
| POP qq | (qq = BC, DE, HL, AF, IX or IY) |
| PUSH qq | (qq = BC, DE, HL, AF, IX or IY) |
| RES b,r | Reset Bit b (b = 0 .. 7, r = B, C, D, E, H, L or A) |
| RES b,(HL) | |
| RES b,(IX + d) | 2 |
| RES b,(IY + d) | 2 |
| RET | Return from Subroutine |
| RET cc | Return if Condition met (cc = NZ, Z, NC, C, PO, PE, P or M) |
| RETI | Return from Interrupt |
| RETN | Return from Non-maskable Interrupt |
| RLA | Rotate Left Accumulator (through Carry) |
| RL r | (r = B, C, D, E, H, L or A) |
| RL (HL) | |
| RL (IX + d) | 2 |
| RL (IY + d) | 2 |
| RLCA | Rotate Left Accumulator, copy bit 7 to Carry |
| RLC r | (r = B, C, D, E, H, L or A) |
| RLC (HL) | |
| RLC (IX + d) | 2 |
| RLC (IY + d) | 2 |
| RLD | Rotate Left BCD |
| RRA | Rotate Right Accumulator (through Carry) |
| RRCA | Rotate Right Accumulator, copy bit 0 to Carry |
| RRC r | (r = B, C, D, E, H, L or A) |
| RRC (HL) | |
| RRC (IX + d) | 2 |
| RRC (IY + d) | 2 |
| RRD | Rotate Right BCD |
| RST p | 6 Call Subroutine (Restart) (p = 0, 8, 16, 24, 32, 40 or 48) |
| RST p,nn | 6 Equivalent to RST p:DW nn |
| SBC A,r | 1 Subtract with Carry (r = A, B, C, D, E, H, L, HX, HY, LX or LY) |
| SBC A,n | 1 n is a byte |
| SBC A,(HL) | 1 |
| SBC A,(IX + d) | 1,2 d is signed displacement |
| SBC A,(IY + d) | 1,2 |
| SBC HL,ss | (ss = BC, DE, HL or SP) |
| SCF | Set Carry Flag |
| SET b,r | Set Bit b (b = 0 .. 7, r = B, C, D, E, H, L or A) |
| SET b,(HL) | |
| SET b,(IX + d) | 2 |
| SET b,(IY + d) | 2 |
| SLA r | Shift Left Arithmetic (r = B, C, D, E, H, L or A) |
| SLA (HL) | |
| SLA (IX + d) | 2 |
| SLA (IY + d) | 2 |
| SLL r | 4 Shift Left and set bit 0 (r = B, C, D, E, H, L or A) |
| SLL (HL) | 4 |
| SLL (IX + d) | 2,4 |
| SLL (IY + d) | 2,4 |
| SRA r | Shift Right Arithmetic (r = B, C, D, E, H, L or A) |
| SRA (HL) | |
| SRA (IX + d) | 2 |
| SRA (IY + d) | 2 |
| SRL r | Shift Right Logical (r = B, C, D, E, H, L or A) |
| SRL (HL) | |
| SRL (IX + d) | 2 |
| SRL (IY + d) | 2 |
| SUB A,r | 1 Subtract (r = A, B, C, D, E, H, L, HX, HY, LX or LY) |
| SUB A,n | 1 n is a byte |
| SUB A,(HL) | 1 |
| SUB A,(IX + d) | 1,2 d is signed displacement |
| SUB A,(IY + d) | 1,2 |
| XOR A,r | 1 (r = A, B, C, D, E, H, L, HX, HY, LX or LY) |
| XOR A,n | 1 n is a byte |
| XOR A,(HL) | 1 |
| XOR A,(IX + d) | 1,2 d is signed displacement |
| XOR A,(IY + d) | 1,2 |
1 Indicates that an alternative short format is available without the A, eg. ADC H is the short version of ADC A,H
2 Indicates a displacement ranging from -128 to +127. The assembler accepts (IX + d), (IX + -d) or (IX - d), similarly for IY. eg. LD B,(IY - 5)
3 Load instructions using HX or LX cannot use H, L, HY or LY as the other register. Similarly, Load instructions using HY or LY cannot use H, L, HX or LX.
4 Indicates an undocumented instruction.
5 The relative address is calculated by the assembler from the supplied absolute address. If the value is outside the range -128 to 127 from the current instruction address plus the two bytes offset fetched by the Z80, the assembler will produce an error.
6 The restart instruction can also use the values 0 to 7 which are multiplied by 8, so RST n is equivalent to RST p where p = n * 8 (n >= 0 and n <= 7). eg. RST 3 is the same as RST #18